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Altera_Forum
Honored Contributor
Honored Contributori have question about verilog. i coudln't make one clock. will u help me please.
i attached file & picure. our team creating uart verilog code. by using modelsim. i have 4 modules for FPGA and one module for simulation as like testbench. so i will explain shortly....
Altera_ForumHonored Contributor
Honored ContributorYou did not initialize the reset value for reg a and reg b in module "dld". Like reg a=0,b =0; Or change the always process like below
always @ (posedge clk or posedge reset) if begin a <= 0; b <= 0; end else begin if(counter == 12'd2604) begin a <= transmit; b <= ~a; end end
