Forum Discussion

KRaut1's avatar
KRaut1
Icon for New Contributor rankNew Contributor
5 years ago

I have created pipeline multiplier and adder schematic in Quartus Prime Lite edition 16.1. During compilation it is giving error "Error (275024): Width mismatch in port "D" of instance "inst12" and type DFF -- source is ""Sum[31..16]""

Other error is: Error (275023): Width mismatch in Sum[31..16] -- source is ""Sum[31..0]" (ID Add32:inst4)" I have named bus "Sum[31..16]" correctly coming to the input B of MUX4X. I don't know why i...
Matin's avatar
Matin
Icon for New Contributor rankNew Contributor
5 years ago

hi. can you help me with this error?

i will send you some screenshots.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

You should really start a new thread for this. Without knowing the functionality of the block, there's no way of knowing why you are getting that error. Post some HDL code or a lower-level schematic design so that folks here can help.