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Altera_Forum
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15 years ago

I got error because of not proper use of std_logic and bit, please help me in solving

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:16:54 02/14/2011 -- Design Name: -- ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I use this ,

signal s : signed(7 downto 0);

....

mul<= mul sra 5;

temp<= to_integer(mul);

but this gives me error defination of operator match here