Forum Discussion
4 Replies
- KhaiChein_Y_Intel
Regular Contributor
Hi Geoffrey,
There is no documentation about the clock speed. Is there timing violation in the design?
Thanks.
Best regards,
KhaiY
- GFros2
New Contributor
I tried a slow clock speed of about 10MHz as I thought the interface was only working at 100KHz. My clock is derived from an HDMI receiver - 130MHz when connected but 40MHz with no video. I have to cope with both.
The real problem with the module is trying to understand how it works. The bytes are all mixed up, address and data, on the avalon side. If the lower two bits of one? of the address bytes is non zereo the part gets locked up and I have to reload the whole design. All I need is an I2C receiver that has a main and sub address along with 16 bits of data to configure various sections of my picture scalar.
Geoffrey
- KhaiChein_Y_Intel
Regular Contributor
Hi Geoffrey,
You may refer to Chapter 16. Intel FPGA I2C Slave to Avalon-MM Master Bridge Core in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf to understand how this IP works.
Thanks.
Best regards,
KhaiY
- KhaiChein_Y_Intel
Regular Contributor
Hi Geoffrey,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best regards,
KhaiY