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TBonn
New Contributor
New ContributorHow to write/read data to DDR3 SDRAM over Avalon-MM Pipeline Bridge
Hello, I'm using the quartus prime standard edition v17.1 to program my terasic tr4 board. Now I wanted to include the DDR3 SDRAM to my project. I create the component with the platform designer. T...
Deshi_Intel
Regular Contributor
Regular ContributorHi Tbonn,
If you are writing your own VHDL design to interact with DDR3 via Avalon MM bus then you need to issue command correctly as per Avalon MM protocol spec requirement.
You can refer to below link for Avalon MM spec
Alternately you can generate DDR3 example design from DDR3 IP. The example design will comes with default RTL traffic generator and checker where you can use to verify DDR3 write/read transaction.
Thanks.
Regards,
Dlim
srinivasan
Occasional Contributor
Occasional Contributorhi desi _intel,
can u share the vhdl code for Avalon_mm to interface with EMIF IP (DDR4) implementation?
