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AZahe1's avatar
AZahe1
Icon for New Contributor rankNew Contributor
6 years ago

How to use the SCLR port of a flip flop in VHDL?

Hi, I am new in VHDL and the Quartus software. I was designing a simple flip flop circuit with synchronous clear by using sequential VHDL, but in the RTL schematic, it looks like it added a multipl...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

You can direct the tool to put the reset to SCLR pin by setting the synthesis setting Force Use of Synchronous Clear Signals=ON ( by default it is OFF).

Use below assignment:

set_global_assignment -name FORCE_SYNCH_CLEAR ON

FYI: By default, tool would turn off the option to use SCLR to because although the usage of SCLR helps to reduce the total number of logic cells used in the design, but it may negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.