How to use "set_clock_groups" properly to constrain 2 asynchronous clocks in different clock domains

Here's what I did. Works as expected.

create_clock -period 20.0 -name CLOCK_50 [get_ports {CLOCK_50}]

create_generated_clock -source {pll|altpll_component|pll|inclk[0]} -divide_by 5 -multiply_by 8 -duty_cycle 50 -name CPUCLK {pll|altpll_component|pll|clk[0]}

create_generated_clock -source {pll|altpll_component|pll|clk[0]} -divide_by 5000 -duty_cycle 50 -name RTCCLK {dk8ea_clock:rtc|rtcclk}

set_clock_groups -asynchronous -group {CLOCK_50} -group {CPUCLK} -group {RTCCLK} -group {altera_reserved_tck}

Note you use the NAME of the clock groups in the set_clock_groups command, not the signal or pin names.