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Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- hi, there. I wrote a document which describes how to access Avalon-Bus in HDL. http://www.akiron.com/fpga/customipmaster.pdf here you can see the document. next step, I will tell you how to read/write memories with using burst transfer. next step is final step of your question. have a nice day. --- Quote End --- Hi. I followed your first instruction, and I have the result as you said. I am trying to do your second instruction, and I have some questions again.. 1. Why do I have to use cpuclock, sdramclock? Why are they separated from mainclock(50Mhz)? (I don't know the reason about 3 clocks) And I can't setup Timer, DLL, so I tried to study about that. 2. What's the difference with Avalon-Master and Avalon-Slave? (I don't know what's the Avalon).. and Why do I use Custom-IP Ram? Can I just use SDRAM or On-chip Memory for data in/out from ram address? For example, can I use only SDRAM address(0x00800000 in your second instruction) instead of Custom-IP & On-chip Memory address(0x00002000 & 0x00002010) in 11 page of second instruction? Thanks for your very kind help.