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SHung4's avatar
SHung4
Icon for New Contributor rankNew Contributor
8 years ago

How to use MACRO on altera modelsim

I add a MACRO on Setting-compiler setting-Verilog HDL input, and it works. But when I run RTL sim by altera modelsim, it seem that it don't use the MACRO. What is the right way to use MACRO on alter...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
8 years ago

Hi,

+define+<macro_name>[=<macro_text>]

I have used simple example

########################CODE##########################

module and_op (a, b, c);

output a;

input b, c;

`ifdef behavioral

wire a = b & c;

`else

or a1 (a,b,c);

`endif

endmodule

##########################CODE####################

​vlog +define+behavioral -work work and_op.v

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)