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SHung4's avatar
SHung4
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8 years ago

How to use MACRO on altera modelsim

I add a MACRO on Setting-compiler setting-Verilog HDL input, and it works. But when I run RTL sim by altera modelsim, it seem that it don't use the MACRO. What is the right way to use MACRO on alter...
SHung4's avatar
SHung4
Icon for New Contributor rankNew Contributor
8 years ago

I write the code in verilog file like this:

----

`ifdef FPGA

.....

`endif​

----

And I can use Setting-compiler setting-Verilog HDL input to add a macro FPGA when synthesis.

But I find that it don't work when run RTL-simulation.