New Contributor
ContributorHello,
DC fifo has completely different interfaces compared to qsys components.
Qsys components use the Avalon interface to interface with the CPU & other components.
So direct use in Platform designer of DCFIFO is not possible.
If you really want to do what you propose then you could build a custom component in Platform designer and use this component as a container for DCFIFO.
On the other hand, if you need FIFO functionality you might want to consider the C++ STL library. There are a number of template classes that do exactly the same but a bit slower than fpga designs.
Best Regards,
Johi.
New ContributorThanks a lot Johi,
Since Im planiing to add it to a custom IP what steps should I take then for adding a Quartus generated IP( I am using Quartus Lite Version)?
Which files are needed so that I can instanatiate it in my custom IP that later could be used in Qsys?
