How to turn off the optimization that removes repeated logic?

You can use the synthesis attribute "Keep Combinational Node/Implement as Output of Logic Cell", this is described on page 16-42 of the 12.1 version of the Quartus Handbook. For verilog, you declare your wire of the node you want to not be synthesized away like this:

wire notout1 /* synthesis keep = 1 */;

assign notout = notin;

Now this instructs the synthesis not to remove the notout1 node, but if it can lump it into the same LUT that implements notin, it may do that, so you may need to declare notin the same way. As people stated before, the delay's are poorly controlled. I've spent some time trying to shove extra gates in for delay to fix timing violations and it never really helped in the end. If you describe why you're doing this there may be a better solution.