Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI assume that this error comes from Quartus and not Modelsim?
The testbench itself should only be included in the Modelsim project and the Quartus project should only contain the design that will go in the FPGA. If you put the testbench as the top level design file in Quartus, it will see that your project doesn't have any inputs or outputs and will conclude that it doesn't need to synthesize anything.