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Benjamin182's avatar
Benjamin182
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4 years ago

How to setup constraint for a PWM DDR output

Hi, I've got a design with a master 100-MHz clock. We need a PWM with a 5-ns resolution. One solution that I've come up with is to use a DDR output block to decrease the resolution from 10 ns to 5...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Ben,


In Qsys, you may refer on how to constraint DDR from the example design when you use DDR IP. You can generates a design example and the design example is a fully-functional example design that can be simulated, synthesized, and used in hardware including the timing constraint if I am correct.