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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to set zero delay path with Quartus II?

Hi, I'm pretty new to Verilog and I'm using Quartus II to try to achieve a zero delay path. I want to add certain delay to some non-free running clock/signal in order to become zero delay path, how ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I think this is not the better way to achieve zero delay, even if you could control optimization, since the overall delay depends non only on synthesis but also on routing.

You'd better use timing constraints on that path and use timing driven synthesis.

I'm not a TimeQuest expert but you probably can do want you need using the set maximum/minimum delay contraints.

Regards