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lkg47's avatar
lkg47
Icon for New Contributor rankNew Contributor
5 years ago

how to set the delay for an asynchronous input

Hello, please help: async port --- "data" pll clk --- clk_1 how to set constraints that define difference between delay lines "data ---> R3|clk" and "data --->R1|d"
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

Why would you use that circuit?

How are you going to use the output of R3? In what clock domain? Are you going to run it thru another dual rank synchronizer to access it in clock domain clk_1? Or what?

set_min_delay and set_max_delay are the sdc primitives you can use to constrain the net delays between the referenced ports.

Never heard of set_data_delay. Where is there a reference to that?