How to set QSYS component base address through VHDL generics

No, the base address column in Platform Designer is the base address of your component as seen from a master connected to your slave. Addresses you set up in your custom component are offsets of this. Remember, every master in the system has its own unique address map. So if you set a base address of, say, 0x1000, in the Platform Designer Base address column, the first register (word) in your component would be accessed by the master at address 0x1000. Depending on the data bus width, the next register (again, word) would be accessed at 0x1002 (for 16-bit data) or 0x1004 (for 32-bit data). The master addressing is byte-wide, which is why I increased by 2 or 4. The slave-side addressing is word-based.

Any generics you use in your custom component code can be optionally customized in the parameter editor when your component is added to the system, but addressing of master-accessible registers in the custom component is not a good idea (or it might even be illegal, not sure). The address map for your component must be fixed at generation time (the End address column in Platform Designer is set by this).

See this online training for all details about creating custom components and their addressing:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html

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