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OKris1's avatar
OKris1
Icon for New Contributor rankNew Contributor
6 years ago

How to set QSYS component base address through VHDL generics

Hi. I am new to QSYS and VHDL, so i am still learning. I have created a VHDL code and simulated it in MODELSIM = it works fine, as it should I have then wrapped it into an avalon MM interface and cr...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

  1. VHDL Generics is not used for base address under system contents tab.
  2. VHDL Generics. VHDL allows the designer to parametrize the entity during the component instantiation.

As you add the components in the Qsys/platform designer system, you specify their base addresses within the span of the address space using Qsys GUI.

Base address can be directly edited by the user, or it can be assigned automatically by using the Assign Base Addresses from System menu

We can control on the offset address using HDL.

Refer below link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qsys_components.pdf

ftp://ftp.intel.com/Pub/fpgaup/pub/Intel_Material/13.1/Tutorials/Making_Qsys_Components.pdf

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

  • OKris1's avatar
    OKris1
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi Anand My custom VHDL code is a basic 2's complement calculator (which for the moment only do multiplication) It has AVALON MM slave interface with 3 registers which are two for input value and one output register for multiplication result When I set a generic value called base_address the first register is given this address, and the second is given base_address+1 and the next one is given base_address+2 I am ot sure if I understand the base column in QSYS system contents tab, but I thought this was the same thing = base_address? When I use Assign Base address from system menu all my QSYS components are given a sequenctially logic address span that do not conflict, but I dont understand how my CUSTOM MADE qsys COMPONENT addressable registers are related to the BASE value in QSYS system contents? Br Øystein ------ Original Melding ------ Fra: "Intel Forums" <supportreplies@intel.com> Til: "oystein.kristiansen@embida.no" <oystein.kristiansen@embida.no> Sendt: 29.05.2019 04.15.07 Emne: AnandRS answered you: How to set QSYS component base address through VHDL generics