Occasional Contributorhow to reset registers in Verilog with minimal resource utilization.
I am using Quartus. I am programming an algorithm in which under certain conditions, certain values should be set to 0.
When I implement synchronous resets for these values, Quartus seems to implement multiplexers sometimes, and sometimes not. I am really trying to minimize resource usage and don't really understand why resets cost so much resources since the registers in the ALMS should have reset pins. What is the mechanic behind this? What should I do to minimize resource consumption?
I have tried the syntax :
-----------------------------
always @(posedge clock)begin
if(reset_condition)begin
value <=0;
end else begin
value <= comb_logic;
end
end
----------------------also
assign value_wire = reset_condition? 0:comb_logic;
always (@posedge clock)begin
value <= value_wire ;
end
----------------------
both ways sometimes increases ALUT usage and sometimes not but are not always equivalent. For example say I have 3x 15 bit variables in my design. At base none of them have resets. If I implement a [? ]reset or an [if else] reset on variable 1, it increases ALUT count by 15. If I implement a[?] reset on variable 2, it also increases ALUT count by 15, but if I use an [if-else] reset on that same variable instead, ALUT count doesnt increase. the third scenario is the opposite for variable 3 where [if else] increases ressources but [?] doesn't
also, would it be viable to & every bit of the input wire with ~(reset condition) to reduce resource consumption?
