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designEngineer's avatar
designEngineer
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

How to report propagation delay from pin to pin with just combinational logic in between

The title basically says it all. If I have just combinational logic between two FPGA pins how can I report the propagation delay of that path in timing analyzer? "report_timing -from [get_ports {inp...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

That's not a constraint, it's a reporting command. OP should still be able to use report_timing.

You have to have some constraints on the I/O. The best and easiest way to do this with with set_max_delay and set_min_delay. If the I/O show up as unconstrained in the unconstrained paths report, report_timing won't work. Once the I/O are constrained, report_timing as you mentioned should work.