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Mahdi's avatar
Mahdi
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

How to reduce IC delay? Useful resources

Hello, I have some basic questions: My design includes a NIOS and an accelerator that is designed by myself. I designed a custom instruction to connect the accelerator and NIOS together. The cus...
skyjuice's avatar
skyjuice
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

I saw that there are only 2 logic levels which are not huge. The IC delay is likely due to the source and destination nodes being placed far away. As a start, are there a lot of fanouts from the source nodes or the combination logic? Or could there be some sort of nodes beyond this path that is pulling them in opposite direction (if you know what I mean)