Forum Discussion
Altera_Forum
Honored Contributor
10 years ago`timescale 1 ns/10 ps
module ht6116_tb();
reg data_set;
reg read_data; // Somewhere to store the data in your test bench
wire data;
reg address;
reg write_enable_n, read_enable_n, chip_select_n, reset;
IDT6116SA15 M1(.IO(data), .A(address), .WE_N(write_enable_n), .OE_N(read_enable_n), .CS_N(chip_select_n), .RESET(reset));
assign data = data_set;
initial
begin
reset = 1'b0;
address = 11'h0;
write_enable_n = 1'h1;
read_enable_n = 1'h1;
chip_select_n = 1'h0;
read_data = 8'h00; // You might want to provision your reg but you don't have to.
# 100;
data_set = 8'h55;
write_enable_n = 1'h0;
# 100;
write_enable_n = 1'h1;
data_set = 8'hzz;
# 100;
read_enable_n = 1'h0;
# 50;
read_data = data; // Read the data in (e.g. half way through your read enable pulse, but can be anywhere whilst read enable is active)
# 50;
read_enable_n = 1'h1;
# 100;
end Cheers, Alex