Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

How to properly constrain SPI - like interface if SCLK freq = FPGA main clk freq

Hi all! My problem looks like wdshen'sproblem in that post: http://www.alteraforum.com/forum/archive/index.php/t-32549.html. But it has some interesting details. My ADC mode is here - (h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Did you get your timings to work properly? If so, can you post your constraints file for others to look at?