How to properly constrain SPI - like interface if SCLK freq = FPGA main clk freq

A PLL also has an internal register structure (not sure if my terminology here is correct...). If you view your design in the RTL Netlist viewer, you would be able the see the hierarchical structure of the pll block. Based on this you can constrain your virtual clock:

create_generated_clock -name "pll_clock" -source { "top level" | alt_pll | sd1 | pll7 | inclk[0] } -divide_by N -multiply_by M { "top level" | alt_pll | sd1 | pll7 | clk[0] }

in this statement the pll clock is derived in the pll7 block, which resides in sd1 block, which resides in the alt_pll module, which resides in the top level. You would see this in RTL viewer. inclk[0] is the system clock you feed to the pll, while clk[0] or [1] or [2] or etc, is the derived output.

in my application the pll clock that I made was 2x the required SPI clock, due to the data recovery algorithm. but your application may be different. In my application I created a clock SPI_SCK_ext that is half the rate of the pll in a register.

The second statement relates this virtual clock to the SCK port that is physically connected to your ADC. Since your CNV and SDO ports are referenced to the SCK port, I created another virtual clock that can tie all of them together.

The second statement basically says that the wire between the derived clock and the SCK port is actually a clock path that you will be referencing other ports too.

Then once this is established, the input and output delays are set with respect to the SCK clock path, and no other clock path. This is important for routing purposes. Basically, you need to make sure that the SCK clock is being derived as close (physically) to the FPGA port as possible, otherwise you will have added latency.

In my application I actually use SPI_SCK_int and SPI_SCK_ext, which technically are the same clock, but allow the fitter to have once clock physically close to the deserializer logic and one clock close to the SCK port.

For your last question: yes my ADC outputs data on falling edge of SCK.

It's hard to say exactly how to write the timing file for your application. In your case the SPI_SCK_ext register is really the output of your pll, so you can simply use the statement above instead of the statement in the previous reply:

create_generated_clock -name SPI_SCK_ext -source [get_pins {"register that is generating clock"|clk}] -divide_by N -multiply_by M [get_pins {"register that is generating clock"|q}]

hope this kinda help you with your constraints. It took me several tries to properly get the constraints correct.