Honored Contributor
Honored ContributorThank you very much for your answer, krasner!
In my current situation, I know PCB delays, Tco of ADC and so on. I wrote the code, and from one compilation to another compilation ADC works or not works. So it is because of delays on FPGA. The problem is, I want to be sure that FPGA delays are constant. Right now I solve the problem like this: 1. I Take into account delays from SCK port and CNV port to ADC and from ADC to SDO port. 2. I Use fast output register for cnv and fast input register for SDO. 3. I can't use the fast output register for SCK, because I use gated clock for SCK like that : (always @ (negedge CLK) enable_sig_ff <= enable_sig; assign SCK = enable_sig_ff & CLK; ) and can't put clock on register's data input. 4. I'm using I/O buffer D3 delay assignment to finely adjust time of SDO input acquisition. 5. I'm using Location assignment for a register "enable_sig_ff" and "&" element, Location choosed near SCK port. But it's not a true way, I want to solve it using proper constraints. So about your advice: 1. Define values - no problem, I know these values. 2. As I know, virtual clock is an external clock, but create generated clock command is for a internally created clocks in FPGA. Also there is no register that generates clock, it comes directly from PLL. So I can't use "get_pins" command. I can use get_keepers and find PLL output and use it as "source" part of command. But I need also to fill the "target" part of command, I don't know exactly what instance to use, I think it should be element "&" output. The second generated clock is port, I don't understand why I need two constraint and can't use one create generated clock command? Could you explain this point again? 3. I need to use set_output_delay command from generated clock to input port SDO and set_output_delay command to output port CS (in my situation CNV) - that is what I need, thank you very much! Also am I right, you used "-clock_fall" option because ADC outputs data on falling edge?
