How to properly constrain SPI - like interface if SCLK freq = FPGA main clk freq

I had a similar issue with a similar type of ADC. What you need to do is account for setup and hold times of the various signals in the ADC (SDO,CS). These are defined in the ADC's data sheet usually by Tsu, Th, and Tco max, Tco min. You also need to account for the PCB trace length at high clock rates like yours - on FR4 signal speed is 6 inches / nanosecond.

Using these values you can write your sdc script.

1) Define values:

set_time_format -unit ns -decimal_places 3

set PCB_dly_max_CS "some# ";# trace delay for CS

set PCB_dly_min_CS "some# ";# trace delay for CS

set PCB_dly_max_SCK "some# ";# trace delay for SCK

set PCB_dly_min_SCK "some# ";# trace delay for SCK

set PCB_dly_max_SDO "some# ";# trace delay for SDO

set PCB_dly_min_SDO "some# ";# trace delay for SDO

set ADC_Tsu_CS "some# ";# setup for falling edge of SCK

set ADC_Th_CS "some# ";# hold for falling edge of SCK

set ADC_Tco_max_SDO "some# ";# Tco for falling edge of SCK

set ADC_Tco_min_SDO "some# ";# min Tco for falling edge of SCK

2) Define the clock source for your ADC. For this you want to create a virtual clock and define its sources. Something like this:

create_generated_clock -name SPI_SCK_ext -source [get_pins {"register that is generating clock"|clk}] -divide_by N -multiply_by M [get_pins {"register that is generating clock"|q}]

note: N and M are how your pll or whatever makes your clock. In your case it would be 1 and 1.

create_generated_clock -name {SPI_SCK_to_ADC} -source [get_pins {"register that is generating the clock signal"|q}] -master_clock {SPI_SCK_ext} [get_ports {SCK}]

3) Using your clocks and delay definitions you can calculate input and output delays:

set_input_delay -clock { SPI_SCK_to_ADC } -clock_fall -min [expr $PCB_dly_min_SDO + $ADC_Tco_min_SDO - $PCB_dly_max_SCK] [get_ports {SDO}]

set_input_delay -clock { SPI_SCK_to_ADC } -clock_fall -max [expr $PCB_dly_max_SDO + $ADC_Tco_max_SDO - $PCB_dly_min_SCK] [get_ports {SDO}]

set_output_delay -clock { SPI_SCK_to_ADC } -clock_fall -max [expr $PCB_dly_max_CS + $ADC_Tsu_CS - $PCB_dly_min_SCK] [get_ports {CS}]

set_output_delay -clock { SPI_SCK_to_ADC } -clock_fall -min [expr $PCB_dly_min_CS - $ADC_Th_CS - $PCB_dly_max_SCK] [get_ports {CS}]

And that's pretty much it: Define delays, define clock source for SCK line, set input and output delays for CS and SDO lines.

Good luck.