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SS5
Occasional Contributor
7 years agoI am not sure whether my design flow is right ?
Please suggest me
module counter ///SUB
(
input clk, enable, rst_n,
output reg[7:0] count
);
always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
count <= 0;
else if (enable == 1'b1)
count <= count + 1;
end
endmodule module Counter_Top_Level_design ///TOP
(
input clk,
input rst_n,
output [7:0] out
);
wire counter_enable;
counter counter_inst (
.clk ( clk ),
.rst_n ( rst_n ),
.enable ( counter_enable ),
.count ( out )
);
// For simulation, use this instantiation:
NIOS_SYSTEM niosii_system_inst (
.clk_clk ( clk ), // clk.clk
.reset_reset_n ( rst_n ), // reset.reset_n
.enable_external_connection_export ( counter_enable ), // output_pio.export
.cout_export ( count )
);
endmoduleNIOS
int result,i;
IOWR(ENABLE_BASE, 0, 0x0); // Enable the counter
alt_printf("Hello from Nios II!\n"); // Send Hello World to the JTAG UART
usleep(100);
for (i=0;i<10000;i++)
{
result=IORD(COUNTER_OUT_BASE, 0);
printf("%d\n",(result+i));
}