How to prevent the user logic/IP netlist of unchanging in SOPC during compilation

I have embedded design which contains nios II processor, user logic, IP, on-chip memory & JTAG UART integrated using Altera SOPC builder. I have optimized my logic module. I don't want to re-adjust my logic module & IP netlists in SOPC tool during re-compilation. how to do it?

Anyone helps is much appreciated.

Thanks