How to perform logical operation for two signal generated at diiferent clock cycle?

This code will give you an idea to implement.

// Design code

module Slave (clk,a,b,counter);

input clk;

input a;

input b;

input [31:0] counter;

reg [8:0] Y;

reg [8:0] storea=0;

reg [8:0] mem1;

reg [8:0] storeb=0;

reg [8:0] mem2;

always @(posedge clk) begin

storea <= {storea[7:0],a};

end

always @(posedge clk) begin

storeb <= {storeb[7:0],b};

end

always @(posedge clk) begin

if(counter == 'd11)

mem1 <= storea;

else if(counter == 'd21)

mem2 <= storeb;

end

always @(counter) begin

if(mem1!== 'dx && mem2 !== 'dx)

Y = mem1 & mem2;

else

Y = 'd0;

end

endmodule

//Testbench code

module TB;

reg clk=0;

reg a=0;

reg b=0;

int counter = 0;

Slave D1 (.clk(clk),.a(a),.b(b),.counter(counter));

always# 1 clk = ~clk;

always @(posedge clk) begin

counter<= counter+1;

end

always @(counter) begin

if(counter >= 2 && counter <= 10)

a = $random;

else if(counter >= 15 && counter <= 20)

b = $random;

else begin

a = 0;b = 0;

end

end

/*always

# 100 a = $random;

# 1450 a = 0;

end

initial begin

# 14350 b = $random;

# 15000 b = 0;

end */

initial

# 100 $finish;

initial

begin

$dumpfile("design.vcd");

$dumpvars;

end

endmodule

Thanks