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Altera_Forum
Honored Contributor
Honored ContributorHow to make some verilog codes invisible in a Quartus project?
I want to protect several critical and quite difficult-designed verilog code segments in a FPGA project, based on Quartus II 15.0 platform. Unfortunately, I don't know how to make them invisible in Q...
Altera_ForumHonored Contributor
Honored ContributorWhat exactly do you mean? Do you have code segments that you don't want to compile? Or are you trying to make the logic invisible?
