How to make delay between states in VHDL state machine?

Okay, so I tried to Fix it by taking a slightly different approach, but it still doeesnt behave the way it should. I'm still very new to VHDL so theres probably some fundamental concept that I'm not understanding.

----------------- CLOCK_start -------------------

library ieee;

use ieee.std_logic_1164.all;

entity Sys_clk is

port

( CLK : in std_logic;

Freq : out std_logic

);

end Sys_clk;

architecture Clock_behave of Sys_clk is

signal counter : integer range 0 to 24000001 := 0;

signal osc : std_logic := '0';

begin

S_reg: process(CLK)

begin

if (rising_edge(CLK))then

counter <= counter + 1;

if (counter = 3000000)then

if (osc = '0') then

osc <= '1';

else

osc <= '0';

end if;

counter <= 0;

end if;

Freq <= osc;

end if;

end process s_reg;

end Clock_behave;

----------------- CLOCK_end -------------------

-------------- Ping Pong_start -------------------

library ieee;

use ieee.std_logic_1164.all;

entity Ping_Pong is

port(

Start, Lb, Rb, CLK : in std_logic;

a,b,c,d,e,f,g,h : out std_logic

);

end Ping_Pong;

architecture Pong_Behave of Ping_Pong is

type state is (wait_s, stopr_s, stopl_s, runr_s, runl_s);

signal pres_s, next_s : state;

signal count : integer range 0 to 10000000 :=0;

begin

State_Logic: process(CLK, start, Lb, Rb )

begin

if(start = '0') then

pres_s <= wait_s;

elsif(rising_edge(CLK)) then

count <= count +1;

case pres_s is

when wait_s =>

next_s <= stopr_s;

count <= 0;

when stopr_s =>

if (Lb = '1' OR Rb = '1')then

next_s <= stopr_s;

count <= 0;

else

if (count = 12)then

next_s <= runl_s;

count <= 0;

else

next_s <= stopr_s;

end if;

end if;

when runl_s =>

if (Lb = '1' OR Rb = '1')then

next_s <= stopr_s;

count <= 0;

else

if (count = 72)then

next_s <= stopl_s;

count <= 0;

else

next_s <= runl_s;

end if;

end if;

when stopl_s =>

if (Rb = '1')then

next_s <= stopr_s;

count <= 0;

elsif (Lb = '1')then

next_s <= stopl_s;

count <= 0;

else

if (count = 12)then

next_s <= runr_s;

count <= 0;

else

next_s <= stopl_s;

end if;

end if;

when runr_s =>

if (Lb = '1' OR Rb = '1')then

next_s <= stopr_s;

count <= 0;

else

if (count = 72)then

next_s <= stopr_s;

count <= 0;

else

next_s <= runr_s;

end if;

end if;

when others =>

next_s <= wait_s;

end case;

pres_s <= next_s;

end if;--start = 0

end process State_Logic;

output_logic: process (pres_s,count)

begin

case pres_s is

when wait_s =>

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

when stopr_s =>

a <= '1'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

when runl_s =>

if (count = 0) then

a <= '0'; b <= '1'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

end if;

if (count = 12) then

a <= '0'; b <= '0'; c <= '1'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

end if;

if (count = 24) then

a <= '0'; b <= '0'; c <= '0'; d <= '1';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

end if;

if (count = 36) then

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '1'; f <= '0'; g <= '0'; h <= '0';

end if;

if (count = 48) then

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '1'; g <= '0'; h <= '0';

end if;

if (count = 60) then

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '1'; h <= '0';

end if;

if (count = 72) then

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '1';

end if;

when stopl_s =>

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '1';

when runr_s =>

if (count = 0) then

h <= '0'; g <= '1'; f <= '0'; e <= '0';

d <= '0'; c <= '0'; b <= '0'; a <= '0';

end if;

if (count = 12) then

h <= '0'; g <= '0'; f <= '1'; e <= '0';

d <= '0'; c <= '0'; b <= '0'; a <= '0';

end if;

if (count = 24) then

h <= '0'; g <= '0'; f <= '0'; e <= '1';

d <= '0'; c <= '0'; b <= '0'; a <= '0';

end if;

if (count = 36) then

h <= '0'; g <= '0'; f <= '0'; e <= '0';

d <= '1'; c <= '0'; b <= '0'; a <= '0';

end if;

if (count = 48) then

h <= '0'; g <= '0'; f <= '0'; e <= '0';

d <= '0'; c <= '1'; b <= '0'; a <= '0';

end if;

if (count = 60) then

h <= '0'; g <= '0'; f <= '0'; e <= '0';

d <= '0'; c <= '0'; b <= '1'; a <= '0';

end if;

if (count = 72) then

h <= '0'; g <= '0'; f <= '0'; e <= '0';

d <= '0'; c <= '0'; b <= '0'; a <= '1';

end if;

when others =>

a <= '0'; b <= '0'; c <= '0'; d <= '0';

e <= '0'; f <= '0'; g <= '0'; h <= '0';

end case;

end process output_logic;

--

end Pong_Behave;

-------------- Ping Pong_end -------------------