How to make delay between states in VHDL state machine?

I suggest using a clock for all of your code. Im guessing you're getting warnings about latches?

There are several problems with the code.

Your sub_clock counter wont work as you think it will because its not in a synchronous process. With your process, it will try and add 1 in a logic loop.

You are missing signals in the sensitivity list for the next state logic. Without the correct list, simulation will not behave like the real hardware (you're missing sub_clock, check, clkevent