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Honored Contributor
Honored ContributorHow to make a FLAG using verilog
Dear Community, I’ve two modules – on is parsing the USART RX signal and the other one is a state machine which shall do something else in case the first module founds e.g. the word “read” inside ...
benc
New Contributor
New ContributorThe code is hard to read, so I did not read it in details. As for the question, normally you would instantiate a register with synchronous set and reset signal. Then you would create these set and reset signals in other synchronous processes (different modules in your case).
