how to legally assign global clock?

When I place and route my entity to Actel A3PE3000 board, I got this error report.

what is the problem? How to fix it?

This is developing environment.

Software: Libero SoC v11.3(not SP1)

Hardware: A3PE3000 pqg484

Language: VHDL

Error report:

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.

Planning global net placement...

Error: PLC004: No legal global assignment could be found. Some global nets have shared

instances, requiring them to be assigned to overlapping global regions.

Global Nets Whose Drivers Are Limited to Quadrants or Which Have No Valid Locations:

|--------------------------------------------|

|Global Net |Valid Driver Locations |

|--------------------------------------------|

|CLK_c |(None)

|--------------------------------------------|

|RST_c |(None)

|--------------------------------------------|

Info: Consider relaxing the constraints for these nets by removing region constraints,

unassigning fixed cells and I/Os, relaxing I/O bank assignments, or using input

buffers without hardwired pad connections.

Error: PLC003: No legal global assignment could be found because of complex region and/or IO

technology constraints.

Error: PLC005: Automatic global net placement failed.

INFO: See the GlobalNet Report from the Reports option of the Tools menu for information about

the global assignment.

The Layout command failed ( 00:00:01 )

The Layout command failed ( 00:00:02 )

Error: Failure when executing Tcl script. [ Line 18 ]

The Execute Script command failed ( 00:00:05 )

Warning: The database was closed without a save, modifications are lost

Design closed.