1) Timing exceptions don't typically affect whether logic is optimized away during compilation. I can't think of a situation where this would be applicable. In fact, timing exceptions usually prevent logic from being optimized away and prevent optimization in some devices (like Stratix 10 and Agilex Hyperflex devices).
2) In the graphical Timing Analyzer tool, you can use the Node Finder in most dialog boxes when you create custom timing reports. The Name Finder lets you search the timing netlist for the resource or path in question similar to using the Node Finder to target nodes or entities for assignments or use in other tools. You set the Name Finder filter to the get_pins collection to find specific pins on a cell (like combout).