Contributor
Super ContributorI'm still not sure what you are looking for. It does seem, though, you are referring to the timing netlist when performing a timing analysis. You can right-click anything and cross-probe to other tools by selecting one of the Locate options. For example, you could cross probe from a timing analyzer report to the RTL Viewer or Technology Map Viewer to see pins on an entity, like a PLL.
ContributorHi sstrell
Yes, like that.
But I don't want to open RTL Viewer or Technology Map Viewer every time.
Like the Design Compile tool on SoC synthesis flow, all register names are named "****_reg".
All output pin of a register is named "****_reg.Q".
All clock pin of a register is named "****_reg.CLK".
The duplicated register's output is named "****_reg~0.Q".
The bit 1 of a register is named "****_reg_1.Q".
It is a naming rule that defined by the tool.
I need it to help people to quickly find the node that they want to.
Back to the PLL on FPGA, there are many pins in PLL module, like follows picture.
I don't know which pin I should constraint.
I don't know which pin I can constraint.
I only know which pin should be constrained the clock constraint from the "drive_pll_clocks" command.
Thank you very much.
