Contributor
Super ContributorI'm still not sure what you are looking for. It does seem, though, you are referring to the timing netlist when performing a timing analysis. You can right-click anything and cross-probe to other tools by selecting one of the Locate options. For example, you could cross probe from a timing analyzer report to the RTL Viewer or Technology Map Viewer to see pins on an entity, like a PLL.
ContributorHi sstrell
Yes, like that.
But I don't want to open RTL Viewer or Technology Map Viewer every time.
Like the Design Compile tool on SoC synthesis flow, all register names are named "****_reg".
All output pin of a register is named "****_reg.Q".
All clock pin of a register is named "****_reg.CLK".
The duplicated register's output is named "****_reg~0.Q".
The bit 1 of a register is named "****_reg_1.Q".
It is a naming rule that defined by the tool.
I need it to help people to quickly find the node that they want to.
Back to the PLL on FPGA, there are many pins in PLL module, like follows picture.
I don't know which pin I should constraint.
I don't know which pin I can constraint.
I only know which pin should be constrained the clock constraint from the "drive_pll_clocks" command.
Thank you very much.
Super ContributorI think you're overthinking this a bit. If your goal is to fully constrain your design for timing, all you need (at a minimum) are clock constraints and I/O constraints. Timing exceptions are optional, though usually required.
For a PLL, the command is derive_pll_clocks (not "drive_pll_clocks") and that command alone defines the output clock domains of the PLL, targeting the output pins of the PLL. They're c0 through c5 in the screenshot you've posted, but the nice thing about the tool and the command is that you don't need to know that to constrain the design. If you add the -create_base_clocks option, that constrains the reference clock into the PLL (inclk0). And with that, you're done (for the clocks that is).
If you are missing constraints, rely on the Unconstrained Paths report from the timing analyzer to find the paths the tool considers to be unconstrained and then constrain them. This report lists unconstrained clock and I/O paths.
ContributorHi sstrell
Thank you, sstrell, very much. I have two questions more.
1. If I use an exception timing constraint on/for a pre-synthesis node, does it work after post-fitter?
Some nodes may is disappeared after post-fitter.
In SoC follow, user always uses the node name which comes from after synthesis.
But I don't know the node name which comes from after post-fitter that can be used for SDC.
2. When I report timing path report, how can directly know the the node name which comes from after post-fitter?
For example, I know the combination output name after post-fitter called "*|combout". So, I can report the specified path delay.
If I don't know that, how can I to directly report the specified path delay?
Thank you very much.
