How to instantiate multiple components with variable number of ports in vhdl?

The problem arrises because the pre_pre_buffer_conv entity requires a connection that is a Generic_ARRAY_type, but it is a different size to the input data type. The initial problem is that xdataout_preprebuffer(i) is a single std_logic_vector that is no_bits wide.

But the connection requires a Generic_ARRAY_type that is no_col_filt entries of std_logic_vector(no_col_fil*no_bits-1 downto 0). So this array dimensions do not map to the input at all.

You need to somehow create a teporary signal inside the entity that will re-map the input array to the required size. It also should not be in a generate loop as it currently is.