How to instantiate a dual RAM with different widths on the R/W port

I don't see a purpose of using a shared variable for RAM inference, also I doubt if it's supported in this place by Quartus? It's never mentioned in the Quartus Handbook.

In the above code, you are trying to write to four consecutive RAM addresses simultanously. This can't work in a single clock cycle.

if rising_edge(clka) then 
--mem(conv_integer(addr_a)) := data_a;
mem(conv_integer(addr_a) * 4+0) := data_a(15 downto 0);
mem(conv_integer(addr_a) * 4+1) := data_a(31 downto 16);
mem(conv_integer(addr_a) * 4+2) := data_a(47 downto 32);
mem(conv_integer(addr_a) * 4+3) := data_a(63 downto 48);
end if;

If you want to emulate different port width's with equal port width RAM, you must do it the other way around: Define the RAM width the larger width and use individual byteenable signals, when writing to the smaller port is intended