How to instantiate a dual RAM with different widths on the R/W port

Quartus II 8.0 fail to infer following code to RAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test_build is

port (

clka : in std_logic;

clkb : in std_logic;

addr_a : in std_logic_vector(6 downto 0);--in natural range 0 to 127;

data_a : in std_logic_vector(63 downto 0);

addr_b : in std_logic_vector(8 downto 0 );--in natural range 0 to 511;

q_b : out std_logic_vector(15 downto 0)

);

end entity;

architecture rtl of test_build is

-- Build a 2-D array type for the RAM

type word_t is array (2**9-1 downto 0) of std_logic_vector (15 downto 0);

shared variable mem : word_t;

signal addr_b_r : std_logic_vector(8 downto 0);--integer;

begin

process(clka)

begin

if rising_edge(clka) then

--mem(conv_integer(addr_a)) := data_a;

mem(conv_integer(addr_a) * 4+0) := data_a(15 downto 0);

mem(conv_integer(addr_a) * 4+1) := data_a(31 downto 16);

mem(conv_integer(addr_a) * 4+2) := data_a(47 downto 32);

mem(conv_integer(addr_a) * 4+3) := data_a(63 downto 48);

end if;

end process;

--rd_addr_t <= std_logic_vector(to_unsigned(addr_b, 9) );

process(clkb)

begin

if rising_edge(clkb) then

addr_b_r <= addr_b;

q_b <= mem(conv_integer(addr_b_r));

-- case (addr_b_r(1 downto 0)) is

-- when "11" =>

-- q_b <= q_t(63 downto 48);

-- when "10" =>

-- q_b <= q_t(47 downto 32);

-- when "01" =>

-- q_b <= q_t(31 downto 16);

-- when "00" =>

-- q_b <= q_t(15 downto 0);

-- when others =>

-- q_b <= x"0000";

-- end case;

end if;

end process;

--q_b <= mem(addr_b_r);

--alt_ram : altsyncram

--generic map (

-- Width_a => 64,

-- width_b => 16,

--

-- widthad_a => 7,

-- widthad_b => 9

--

--)

--port map (

--

-- clock0 => clka,

-- clock1 => clkb,

--

-- data_a => data_a,

-- address_a => std_logic_vector(to_unsigned(addr_a, 7) ),

--

-- address_b => std_logic_vector(to_unsigned(addr_b, 9) ),

-- q_b => q_b

--

--);

end architecture rtl;

As Tricky posted, it's not a bad idea to add muxes on the output, like the quoted part using "case" above. U need to asure the width of R/W ports is same, as well as the address.