Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to instantiate a dual RAM with different widths on the R/W port

Hi, the dual RAM: Write port：128×16－bits reading port： 2048×1－bit I pefer HDL design input such VHDL or Verilog， please DO NOT tell me to instantiate th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

For your second port, use an address translation and bit selection from 16 to 64 in an upper module.

--- Quote End ---

Thats fine, but its not as elegant as the direct instantiation - it will add muxes on the output. Its not terrible, just not as compact.