How to instantiate a dual RAM with different widths on the R/W port

Example from application note 226:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY dualport_ram IS
  PORT (
    data_out : OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
    data_in  : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
    wr_addr  : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    rd_addr  : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
    we       : IN STD_LOGIC;
    clk      : IN STD_LOGIC);
END dualport_ram;
ARCHITECTURE ram_infer OF dualport_ram IS
  TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (63 DOWNTO 0);
  SIGNAL mem: Mem_Type;
  SIGNAL addr_reg: STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
  data_out <= mem (CONV_INTEGER(rd_addr));
  PROCESS (clk, we, data_in)
  BEGIN
   IF (clk=’1’ AND clk’EVENT) THEN
      IF (we=’1’) THEN
        mem(CONV_INTEGER(wr_addr)) <= data_in;
      END IF;
    END IF;
  END PROCESS;
END ram_infer;