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Altera_Forum
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16 years ago

How to instantiate a dual RAM with different widths on the R/W port

Hi, the dual RAM: Write port：128×16－bits reading port： 2048×1－bit I pefer HDL design input such VHDL or Verilog， please DO NOT tell me to instantiate th...
Altera_Forum's avatar
Altera_Forum
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16 years ago

This is the point, you cannot currently infer a memory with missmatched in/out port sizes. The code was one suggested way it "might" be done.

The synthesiser would have to look at the behaviour around the code rather than the declarations, to infer the memory correctly.