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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to instantiate a dual RAM with different widths on the R/W port

Hi, the dual RAM: Write port：128×16－bits reading port： 2048×1－bit I pefer HDL design input such VHDL or Verilog， please DO NOT tell me to instantiate th...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I am not sure if this would work

type mem_t is array(0 to 511) of std_logic_vector(15 downto 0);

signal mem : mem_t;

Won't this still infer a memory that is 16 bits wide on both ports?

I guess the inference rules for memories are ambiguous and tool dependent.

The "not to be named" mega-function wizard seems the safest way;)