How to instantiate a dual RAM with different widths on the R/W port

Something like this? (this infers dual port ram fine when addr_a/b and data_a/q_b sizes match) :

entity test_build is
    
    
    port (
      clka       : in std_logic;
      clkb       : in std_logic;
      
      addr_a     : in natural range 0 to 127;
      data_a     : in std_logic_vector(63 downto 0);
      
      
      addr_b     : in natural range 0 to 511;
      q_b        : out std_logic_vector(15 downto 0)
      
    );
end entity;
architecture rtl of test_build is
  type mem_t is array(0 to 511) of std_logic_vector(15 downto 0);
  signal mem    : mem_t;
  
  signal addr_b_r : integer;  
  
begin
  
  process(clka)
  begin
    if rising_edge(clka) then 
      mem(addr_a*4)     <= data_a(15 downto 0);
      mem(addr_a*4+1)   <= data_a(31 downto 16);
      mem(addr_a*4+2)   <= data_a(47 downto 32);
      mem(addr_a*4+3)   <= data_a(63 downto 48);
    end if;
  end process;
  
  process(clkb)
  begin
    if rising_edge(clkb) then
      addr_b_r <= addr_b;
    end if;
  end process;
  
  q_b  <= mem(addr_b_r);
  
  
  --alt_ram : altsyncram
  --generic map (
  --  Width_a    => 64,
  --  width_b    => 16,
  --  
  --  widthad_a  => 7,
  --  widthad_b  => 9
  --  
  --)
  --port map (       
  --  
  --  clock0         => clka,
  --  clock1         => clkb,
  --  
  --  data_a         => data_a,
  --  address_a      => std_logic_vector(to_unsigned(addr_a, 7) ),
  --  
  --  address_b      => std_logic_vector(to_unsigned(addr_b, 9) ),
  --  q_b            => q_b
  --  
  --);
  
  
end architecture rtl;