How to instantiate a dual RAM with different widths on the R/W port

Ive had this very problem myself:

Solution: Either use the megawizard or include the altera_mf library and instantiate an altsyncram manually. Unfortunately this is no way to infer an altsyncram with different sized in and out ports, and had it confirmed from altera themselves. I have raised it as an enhancement request, so if enough people ask for it, maybe it will appear one day.

As a point of note: Xilinx, synopsis and Mentor tools cant do it either.