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Altera_Forum
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16 years ago

How to instantiate a dual RAM with different widths on the R/W port

Hi, the dual RAM: Write port：128×16－bits reading port： 2048×1－bit I pefer HDL design input such VHDL or Verilog， please DO NOT tell me to instantiate th...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Altera altsyncram MegaFunction is actually the low level primitive used by Quartus, when inferring RAM from HDL code, you may want to check the physical mapping of your designs. It can be also instantiated in HDL directly, which is, as far I'm aware of, the only way to create dual port RAM with different width. At least, I'm usually going this way. As far as I understand, you don't want to hear about.