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Altera_Forum
Honored Contributor
10 years agoTricky made plenty analysis as usual.
it is school project, perhaps such structure is described in task. We don't know. I see 7bit adder without reset, I see 2 components with tri-state when you can make multiplexer if they really have the same outputs. I see output signals from FSM not defined in each state. Better to move them out and make selected assignments some kind of decoder. really it is difficult to say that one has FSM with output signal for control only. be as much simple as you can until you get wire when you await register.