How to initial onchip_memory in modelsim post-simulation?

Well, routing debug signals to your top-level interface is a way to debug internal points in your post-fit netlist without hunting for and grouping together the individual nodes that comprise your "point of interest", which can be damn near impossible without inside knowledge about the way the compiler optimizes a design. An arbitrary hierarchical reference into your original RTL will be most likely be invalid after compilation. Still, you've hit upon a good technique for debugging your RTL more deeply within your Verilog testbench itself. In VHDL, you're simply stuck with adding internal nodes to the waveform viewer or manually routing them to the design boundary, even when debugging just the RTL.