How to initial onchip_memory in modelsim post-simulation?

Great answer... You correct my direction:)

BTW, I have found the methods to allows access to any signal from any other hierarchical block without having to route it via the interface in modelsim.

The answer locates in Chapter 9 signal spy in Modelsim User's Manual.

The following is the introduction of this chapter, FYI.

The Verilog language allows access to any signal from any other hierarchical block without

having to route it via the interface. This means you can use hierarchical notation to either

assign or determine the value of a signal in the design hierarchy from a testbench. This

capability fails when a Verilog testbench attempts to reference a signal in a VHDL block

or reference a signal in a Verilog block through a VHDL level of hierarchy.

This limitation exists because VHDL does not allow hierarchical notation. In order to

reference internal hierarchical signals, you have to resort to defining signals in a global

package and then utilize those signals in the hierarchical blocks in question. But, this

requires that you keep making changes depending on the signals that you want to reference.

The Signal Spy procedures and system tasks overcome the aforementioned limitations.

They allow you to monitor (spy), drive, force, or release hierarchical objects in a VHDL or

mixed design.